This invention relates to the field of ferroelectric memory integrated circuit processing. In particular, the invention relates to forming protective layers on top of top electrodes of ferroelectric capacitors in ferroelectric memory integrated circuits.
The potential of ferroelectric random access memory (FRAM) as the preferred memory technology for handheld electronic devices like cellular telephones, personal digital assistants (PDAs), and digital cameras has long been recognizedxe2x80x94FRAM is a nonvolatile memory technology that does not lose data when power is shut off. In contrast, the data stored in the volatile DRAM memory used in most desktop and notebook computers is lost when the computer is shut down. These computers require an additional component, such as a bulky and delicate hard disk drive, to retain data between power ups. Thus, FRAM helps keep handheld devices small and durable by eliminating the need for additional, nonvolatile data storage components.
FRAM has several advantages over other nonvolatile memory technologies such as electrically erasable, programmable read only memory (EEPROM) and flash EEPROM. EEPROM and flash EEPROM tend to have short read times, ranging between nanoseconds and microseconds, but write times on the order of milliseconds. The several orders of magnitude difference between read and write times, combined with the block-erase character of flash EEPROM, can complicate the design and use of EEPROM and flash EEPROM devices. In contrast, FRAM can execute both read and write operations in less than one microsecond.
FRAM also has excellent endurance characteristics: the useable lifetime of FRAM memory cells can extend to more than a trillion (1012) read/write cycles. Such strong resistance to read/write cycle fatigue makes FRAM well suited for devices like portable computers that execute hundreds of millions to billions of operations per second.
FRAM memory cells are formed by capacitors such that data is accessed by manipulating the voltage and/or current applied to electrodes of the capacitors. The capacitors in FRAM memory cells use ferroelectric compounds to separate the electrodes. Ferroelectric compounds commonly used in FRAM include oxides with a perovskite crystal structure such as lead titanate zirconate-Pb(ZrxTi1xe2x88x92x)O3xe2x80x94commonly referred to as PZT, and strontium bismuth titanate-SrBiTiOxe2x80x94commonly referred to as SBT. These ferroelectric dielectric materials are integrated with other semiconductor devices to provide circuitry for addressing, selection, and control logic. Unfortunately, the desired electrical characteristics of many ferroelectric materials, such as data retention and resistance to fatigue, are degraded under typical semiconductor processing conditions. Thus, semiconductor device manufacturers face continual difficulty in preserving the high quality electrical characteristics of ferroelectric materials when integrating FRAM memory cells with standard semiconductor production and packaging processes.
One of the primary reasons for the degradation of FRAM during processing is believed to be the reaction of oxygen atoms in the ferroelectric material with gases such as hydrogen. Hydrogen exposure occurs during cleaning operations like plasma ashing to remove photoresists. Also, metal deposition processes often incorporate hydrogen through the use of organometallic compounds and/or the use of hydrogen to treat formed metal structures. Moreover, it is common in semiconductor-manufacturing processes to remove excess material after a deposition by chemical mechanical polishing (CMP). While CMP is effective for removing excess materials such as tungsten, the chemical reactions and mechanical agitation are also believed to drive hydrogen into the ferroelectric layer and damage the PZT. Consequently, the resulting FRAM produced has much poorer and inconsistent quality than desired.
The present invention is directed to an integrated circuit and methods for making an integrated circuit that include ferroelectric components integrated with other semiconductor devices that provide improved performance and greater process latitude. The present invention provides for forming a protective cap layer comprising conducting perovskite or layered perovskite material on the top electrode of a ferroelectric capacitor in order to protect the underlying layer (or layers) of ferroelectric materials from chemical degradation by hydrogen and other reduction gases.
In accordance with the present invention there is provided an integrated semiconductor device that comprises a ferroelectric capacitor, where a protective cap layer, comprising strontium-ruthenium-oxide (SRO), is deposited over the top electrode of the capacitor. The SRO cap layer protects the ferroelectric dielectric layer of the capacitor from chemical and mechanical degradation during semiconductor fabrication processes. In particular, the cap layer is thought to hinder the migration of hydrogen through the top electrode and into the ferroelectric dielectric layer, where it degrades the ferroelectric dielectric materials such as PZT.
Further in accordance with the present invention, there is also provided a method for forming the SRO cap layer on the top electrode of a ferroelectric capacitor. In this method, the SRO cap layer is annealed twice after being deposited on the top electrode: First, the cap layer, originally deposited in an amorphous phase, is annealed in a non-oxidizing atmosphere at a temperature of 500xc2x0 C. to 700xc2x0 C. in order to crystallize the SRO. Then, the crystallized SRO cap layer is annealed again, only this time in an oxidizing atmosphere at a temperature of 300xc2x0 C. to 500xc2x0 C. The resulting crystallized, oxygen annealed SRO cap layer provides the underlying ferroelectric dielectric layer with excellent protection from hydrogen degradation during subsequent device fabrication steps.
The ferroelectric capacitor structure provided by the present invention is more robust in the face of subsequent temperature and chemical exposure during annealing, cleaning, multi-layer metal processing, interconnect processing and assembly. Moreover, the adverse impact of processes subsequent to fabrication of the capacitor structures is reduced, enabling a wider variety of processes to be performed subsequent to fabrication and thereby enabling new devices with higher levels of integration to be achieved without compromising the performance of the ferroelectric devices.